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EM250
Receiving a character always causes a serialization of a transmit character pulled from the transmit FIFO.
When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit FIFO) and the register
bit INT_SCTXUND in the INT_SC2FLAG register is set. Because there is no character available for serialization,
the SPI serializer retransmits the last transmitted character or a busy token ( 0xFF ), which is determined by
the register bit SC_SPIRPT in the SC2_SPICFG register.
Note:
Even during a transmit underrun, the register bit SC_SPITXIDLE in the SC2_SPISTAT register will
clear when the SPI master begins to clock data out of the MISO pin, indicating the transmitter is not
idle. After a complete byte has been clocked out, the bit SC_SPITXIDLE will be set and the register
bit INT_SCTXIDLE in the INT_SC2FLAG interrupt register will be set. The bits SC_SPITXIDLE and
INT_SCTXIDLE will toggle in this manner for every byte that is transmitted as an underrun.
When a transmit character is written to the (empty) transmit FIFO, the SC2_SPISTAT register and the
INT_SC2FLAG register do not change. Further transmit characters can be written to the transmit FIFO until it
is full, which causes the register bit SC_SPITXFREE in the SC2_SPISTAT register to clear. When the SPI
master begins to clock data out of the MISO pin, the register bit SC_SPITXIDLE in the SC2_SPISTAT register
clears (after the first bit is clocked out) and indicates that not all characters are transmitted yet. After
shifting one full transmit character to the MISO pin, space for one transmit character becomes available in the
transmit FIFO. This causes the register bit SC_SPITXFREE in the SC2_SPISTAT register to be set. After all
characters are shifted out, the transmit FIFO is empty, which causes the register bit SC_SPITXIDLE in the
SC2_SPISTAT register to be set.
The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO
into the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of padding,
0xFF, onto the start of transmit data. This byte of padding is only inserted when slave select is deasserted,
the FIFO is empty, and the transmitter (serializer) is idle. An idle transmitter is indicated by the
SC_SPITXIDLE bit in the SC2_SPISTAT register. Subsequent transmissions while slave select remains asserted
do not include a byte of padding. But, if any new data is written to the transmit FIFO while slave select is
deasserted, the first byte immediately goes into the transmit serializer without waiting for clocks from the
external SPI master. The transmit serializer will still hold this data until there are clocks from the master.
Because the data goes directly into the serializer, there is a race condition between when the data enters the
serializer and when the SPI master attempts to clock out the data. If the data enters the serializer after the
SPI master begins clocking data, then a byte of padding is transmitted as described above. If the data enters
the serializer before the SPI master begins clocking data, then the first byte of data is transmitted without a
byte of padding. Because of this race condition and the inability of the SPI master to know the current,
internal state of the EM250, it is best to design a protocol around SPI slave interaction that handles this race
condition and avoids potential issues. Some possible protocol solutions are:
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SPI slave does not place data into the transmit FIFO until the SPI status indicates that the SPI master has
begun clocking data. One possible indication of this is the SC_SPIRXVAL bit.
The communications between the SPI master and SPI slave use an interrogation-response scheme where
the SPI slave only queues up data for transmission after receiving data from the master, without slave
select deasserting between the two events.
SPI slave begins all transmissions with its own byte of padding, such that the master always receives one
or two bytes of padding.
The data from SPI slave includes a data integrity scheme where the information received by the master
can be validated as accurate.
Interrupts are generated by one of the following events:
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Transmit FIFO empty and last character shifted out (0 to 1 transition of SC_SPITXIDLE )
Transmit FIFO changed from full to not full (0 to 1 transition of SC_SPITXFREE )
Receive FIFO changed from empty to not empty (0 to 1 transition of SC_SPIRXVAL )
Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B )
Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B )
Received and lost character while receive FIFO was full (Receive overrun error)
Page 65
120-0082-000V Rev 1.1
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EM250-COMP-XIDE 制造商:Silicon Laboratories Inc 功能描述:COMPILER XIDE FOR EM250 1SEAT
EM250-DEV 功能描述:KIT DEV FOR EM250 RoHS:否 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:InSight 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796
EM250-EK-R 功能描述:KIT EVAL EM250 RF TEST RoHS:是 类别:RF/IF 和 RFID >> 过时/停产零件编号 系列:InSight 标准包装:1 系列:- 类型:用于 200/300 系列的欧盟开发套件 适用于相关产品:Zensys RF 模块 所含物品:开发板，模块，编程器，软件，线缆，电源 其它名称:703-1019Q3225667
EM250-JMP-R 功能描述:KIT JUMP START FOR EM250 RoHS:否 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:JumpStart 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796
EM250-RCM-R 功能描述:EM250 RCM BOARD RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796
EM250-RTR 功能描述:IC ZIGBEE SYSTEM-ON-CHIP 48-QFN RoHS:是 类别:RF/IF 和 RFID >> RF 收发器 系列:EM250 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:30 系列:- 频率:4.9GHz ~ 5.9GHz 数据传输率 - 最大:54Mbps 调制或协议:* 应用:* 功率 - 输出:-3dBm 灵敏度:- 电源电压:2.7 V ~ 3.6 V 电流 - 接收:* 电流 - 传输:* 数据接口:PCB，表面贴装 存储容量:- 天线连接器:PCB，表面贴装 工作温度:-25°C ~ 85°C 封装/外壳:68-TQFN 裸露焊盘 包装:管件
EM250-STACK-R 制造商:Silicon Laboratories Inc 功能描述:EM250 BOARD STACK (RCM + BREAKOUT) - Boxed Product (Development Kits) 制造商:Silicon Laboratories Inc 功能描述:BOARD STACK EM250 RCM & BREAKOUT
EM25-12V-DC 制造商:ECLIPSE MAGNETICS 功能描述:HOLDING ELECTRO MAGNET